Syllabus
Integrated Circuit Layout and Design I

Integrated Circuit Layout and Design I

DFTG-2470

Summer 2013
05/28/2013 - 08/13/2013

Course Information

Section 001
Lecture
MW 17:30 - 21:20
NRG3 3222
Casey Wesolick

Office Hours

  • M W
    5:00pm - 5:30pm
    By Appointment

Course description

An introductory course in the layout and design of integrated circuits. This is the first of three courses designed to train students to become IC Layout Designers; however, this course may also be taken as a technical elective for other degree plans. An overview of the IC design and manufacturing process is provided with an emphasis on CMOS technology. Students learn to interpret logic gate symbols as well as the schematics of basic circuits. Instruction includes helping students to construct layouts beginning with the simple and progressing to the complex. Students receive training in Cadence Virtuoso to compose their layouts. To insure proper layout construction both physically and electrically, DRC and LVS verification is introduced.

Course Requirements

Text

IC Layout Basics Christopher Saint / Judy Saint


Materials

Colored pencils
Graph paper
Binder


Prerequisites

DFTG 2419, DFTG 1458, or Instructor approval.

May be taken concurrently with CETT 1409. CETT 1425 recommended.

 

Projects

P-channel transistor
N-channel transistor

Inverter
Multi-leg P-channel transistor
Two-input NOR
Three-input NAND
Transmission Gate
Flip-Flop
Shift Register
Latch
Tri-State Inverter
Bonding Pad
Input Protection
Input Buffer
Complex Gate
Top Level Chip

Course Subjects

Class 1

Introduce Integrated Circuits and Design Rules

 

Class 2

Introduce PMOS & NMOS schematics, cross-sections and layouts

Projects: PMOS & NMOS layouts

PMOS & NMOS questions

 

Class 3

Introduce Cadence Virtuoso

 

Class 4

Introduce Stick Diagrams; Inverter schematic and layout;  Folding and Sharing Transistors

Projects: Inverter layout & Folding Transistor layout

Inverter & Folding and Sharing questions

 

Class 5

Introduce NOR & NAND schematics and layouts

Projects: NOR & NAND layouts

NOR & NAND questions

 

Class 6

Continue NOR & NAND layouts

 

Class 7

Introduce Transmission Gate schematic and layout

Project: Flip-Flop layout

 

Class 8

Continue Flip-Flop layout

 

Class 9

Introduce Latch schematic and layout

Project: Latch layout

 

Class 10

Review for Mid-Term Exam

Continue Latch layout

 

Class 11

Mid-Term Exam

 

Class 12

Introduce Capacitor schematic and layout

Project: Shift Register layout

 

Class 13

Continue Shift Register layout

 

Class 14

Introduce Guard Rings; Tri-State Inverter schematic and layout

Project: Tri-State Inverter layout

 

Class 15

Introduce Resistor schematic and layout; Input/Output Circuits

Projects: Input Protection, Pad and Input Buffer layouts

 

Class 16

Introduce Complex Gate schematic and layout

Project: Complex Gate layout

 

Class 17

Continue Complex Gate layout

 

Class 18

Introduce Final Project schematics and layout

 

Class 19

Continue Final Project

 

Class 20

Continue Final Project

 

Class 21

Review for Final Exam

Continue Final Project

 

Class 22

Final Exam

Student Learning Outcomes/Learning Objectives

Recognize schematic symbols for basic CMOS devices
Identify the components in the CMOS transistor cross-section
Translate design schematics into layout architecture
Select proper layers & coordinate placement of these layers in relationship to each other in accordance with design rules
Fold transistors when their width exceeds maximum value or as appropriate to the design
Share diffusion as appropriate
Minimize transistor drain area
Properly connect circuit nodes with metal lines of sufficient dimension to carry the current load
Maximize contact and via cuts as appropriate
Insure sufficient substrate and well ties (taps) exist
Place text in the layout as required by the schematic
Translate resistor values to appropriate layout dimensions
Minimize the area required for a given circuit
Efficiently use Cadence Virtuoso to construct layout
Utilize design hierarchy to build cells containing subcells
Recognize the components that are required to build a complete chip

Grade Determination

Daily Work   50% of final grade
Mid-Term Exam   25% of final grade
Final Exam   25% of final grade

Daily Work shall consist of warm-ups, drawing assignments, questions
and possible quizzes. Grades will reflect the quality of work performed within
the assigned time period.